At the present time, semiconductor circuitry (comprising one or more microchips, or parts thereof) is generally designed by a multi-stage process. Initially, a hardware designer will specify the function of the semiconductor circuitry at a system level. For example, they may define the function of the semiconductor circuitry in a language such as C, C++, System C, or through a modelling software package such as MatLab (MatLab is a Trade Mark). This architectural modelling process may also be carried out in a hardware description language (see below). System level design includes specification of the semiconductor circuitry at a modular level, and determination of outputs of the semiconductor circuitry, or modules thereof, in response to a given sequence of inputs.
Thereafter, a semiconductor circuitry designer will specify the structure of the semiconductor circuitry in the form of a hardware description language (HDL). At the present time, the most commonly used HDLs are Verilog and VHDL (Verilog and VHDL are Trade Marks). Verilog is specified in IEEE Computer Society Standard 1364.1 (1364.1 is a Trade Mark). HDLs can be used to specify the function of semiconductor circuitry at register transfer level (RTL). An RTL model defines the behaviour of the semiconductor circuitry at the level of individual registers, including their interconnection and the logic which determines how the values of the registers change during operation of the circuitry. HDLs such as Verilog can include code of at least two types. Firstly, the synthesisable subject of the language which specifies an RTL model of the semiconductor circuitry being designed. Secondly, HDLs can include other language which is executable, along with the synthesisable subset, by a simulation program. For example, it is common practice to use an HDL to define a “test harness” which provides an interface and specifies data to be input to simulated semiconductor circuitry. Test harnesses can also be developed in specialised languages such as Vera and Specman E (Vera and Specman E are Trade Marks).
The next stage in semiconductor circuitry design is to use the RTL model to specify the structure of the semiconductor circuitry at gate level, i.e. in the form of logic gates and their interconnections, a so-called netlist. This process is semi-automated by synthesis software applications. Gate level logic is then used to specify the precise layout of the logic gates on a semiconductor wafer, and to then prepare masks for use in the fabrication of one or more microchips. Again, this process is semi-automated using software applications.
It is both costly and time-consuming to prepare masks and manufacture semiconductor circuitry. It is therefore economically vital to test semiconductor circuitry, and verify its design, prior to specifying masks and fabricating the microchips.
Furthermore, there are many circumstances in which it is desirable to simulate the function of semiconductor circuitry on a computer. For example, microchips including both one or more microprocessors and embedded software, a configuration referred to as system on a chip (SOC), require simulation during and after their design process. Simulations of SOCs and other semiconductor circuitry are of benefit both to the programmers whose role it is to develop the embedded software, and both software and hardware designers wishing to develop systems including the SOCs.
It has been known for some time how to simulate the function of semiconductor circuitry by simulating the RTL model. Although such simulations are generally accurate, as RTL models fully define the function of semiconductor circuitry, this process is slow.
VTOC (VTOC is a Trade Mark), available from Tenison Technology EDA Limited (Cambridge, England), is a software application which compiles a register transfer level description of a semiconductor into a software emulator of semiconductor circuitry, in a computing language, such as C, C++ or SystemC. The resulting emulator of a semiconductor can be linked to other computer programs, compiled, and used by systems developers, and developers of embedded code, to accurately simulate the function of the emulated semiconductor circuitry during the design process.
However, the validity of a software emulator of semiconductor circuitry is critically dependent on it being verifiable that the software emulator provides the same output in all relevant circumstances as an RTL model derived from the same HDL code.
It is therefore an object of the present invention to provide a method of verifying that two simulations of semiconductor circuitry are equivalent. Specific embodiments of the present invention aim to verify that a software emulation of semiconductor circuitry is equivalent to an RTL model of the same circuitry.
When an HDL model of a microchip is simulated, it is normal practice to generate a trace file. A common standardised trace file format at the present time is VCD (value change dump), specified in IEEE standard 1364, as amended from time to time. HDLs typically include specifications of trace files. Verilog VCD details in time order, the values of inputs, outputs, registers and some wires in the simulated semiconductor circuitry. By analysis of a trace file, a designer can check the function of a model. Wave trace viewer programs are used by engineers to view the changes in input, output, register and wire values with time.
A separate trace file can be output by a software emulator of semiconductor circuitry, but only if a suitable test harness is prepared for use with the software emulator. However, it can be very difficult to prepare a suitable test harness to drive a software emulator using data which can be shown to be equivalent to that generated by the HDL test harness used to drive the HDL definition of semiconductor circuitry during RTL simulation and produce the trace file. One approach that is known is to interface the test harness specified in the HDL language from which the RTL trace file was prepared with the software emulator. Such a test harness can be interfaced with a software emulator of semiconductor circuitry written in for example, C, using an interface such as PLI. This is very difficult to do in practice. Furthermore, if an error is generated during such a simulation, there is no easy way to know where or when within the simulation the error took place.
Accordingly, it is an object of some embodiments of the present invention to simplify the process of running a software emulator of semiconductor circuitry within a test harness, particularly one which is specified in a hardware definition language. Such embodiments aim in particular to allow a software emulator of semiconductor circuitry produced from an RTL description of semiconductor circuitry to be executed within the same test harness as has been prepared for testing the RTL description.
It is a further object of some embodiments of the present invention to enable a comparison as to whether two simulations of semiconductor circuitry are equivalent to be carried out, which allows the location and simulator time at which an error indicating non-equivalence takes place to be determined.
There are various other reasons why a trace file output by a software emulation of semiconductor circuitry, such as VTOC, cannot readily be compared with a VCD trace file of an RTL model.
For example, one problem faced in comparison of a trace file in VCD format (or similar format) from simulation of an RTL model, and a software emulator of semiconductor circuitry such as VTOC is that registers and wires may be defined a plurality of times in the same VCD file. For example, a 32 bit register may be defined using the $var declaration and one or more individual bits of this vector may be declared again, with different identifiers. Thus, the same register or part thereof may be output several times in a trace file, with different identifiers whenever it is updated. It is difficult to deal automatically with these aliases.
Furthermore, the VCD format allows value changes which take place at the same time to be output in any order. Therefore, strict comparison of the output of two trace files could identify errors which are simply due to the ordering in which simultaneous value changes are presented.
Software emulators of semiconductor circuitry, such as VTOC models, achieve an improvement in execution speed over RTL models in several ways. One particular way in which this is achieved in some implementations (for example, VTOC) is by use of a cycle-accurate model. Unlike an RTL model which specifies changes in the values of registers which take place during clock cycles, a cycle-accurate software emulator of semiconductor circuitry outputs the values of registers only at the beginning/end of successive clock cycles. A second method by which such models may achieve an improvement in execution speed over RTL model simulators is by providing a two-state output, i.e. an output consisting only of logical 0's and 1's. This is in contrast to RTL models which typically also include metalogical values, x (undefined) and z (undriven). In addition, software emulators may not model the values of any wires which may be contained in an RTL model (or may create new variables with no corresponding signal in the RTL model).
Thus, the VCD produced by a simulation of an RTL model and the trace file of a software emulator such as VTOC cannot be readily compared.
Accordingly, it is difficult to verify that an RTL model and a software emulator of semiconductor circuitry are equivalent.
It is therefore an object of the present invention to provide a method of verifying an RTL model and a software emulator of semiconductor circuitry, applicable where the software emulator includes one or more of the features of being cycle-accurate, having a two-state output, excluding wires from its model, or including variables which are not equivalent to signals in an RTL model.